Without limiting the scope of the invention, its background is described in connection with the most widely used electrically-erasable, electrically-programmable, read-only cell which is an n channel field effect transistor with an additional floating gate structure disposed between the channel and the control gate, for example, by charging the floating gate with electrons, a logic "0" can be programmed into the cell, while allowing the floating gate to remain uncharged programs logic "1". This is due to the fact that the charge on the floating gate shifts the threshold voltage above which the control gate must be raised to induce current flow in the channel, thereby determining whether a current will be sensed between the source and the drain when reading voltages are applied therebetween.
Heretofore, in this field, EEPROM cells have generally been fabricated as stacked structures with the source and drain regions formed in the face of the substrate, the floating gate vertically spaced from the intervening channel by a layer of oxide and the control gate vertically spaced from the floating gate by another layer of oxide. In the array configuration, the source and drains are elongated to define a plurality of columns and the control gates are elongated to define a plurality of rows of cells. The basic structure of a conventional EEPROM cell in essence comprises a five level stack.
The stack configuration of conventional EEPROM cells has significant drawbacks when such cells are fabricated, especially in the normal situation when the cells are fabricated as part of an array. To achieve optimum operating efficiency while maintaining high cell density, the edges of the floating gates and the overlying control gates must be precisely aligned. To obtain precise alignment, the face of the workpiece must be precisely masked and a stack etch performed to define the floating gates, the control gates and the oxide layers. The precision required in the mask/stack etch process adds further complexity to the overall fabrication process of an array of EEPROM cells.
Thus, a need has arisen for a EEPROM cell which does not employ the conventional stacked EEPROM structure and which is not subject to the disadvantages inherent in the fabrication of such cells.